Locked loop circuits, such as phase locked loop circuits, are basic components of radio, wireless, and telecommunication technologies. A phase locked loop or phase lock loop (PLL) is a control system that generates an output signal having a phase related to the phase of an input signal. A simple PLL includes a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of a reference periodic signal, adjusting the oscillator to keep the phases matched. Keeping the input and output phase in lock step also implies keeping the input and output frequencies the same. Consequently, in addition to synchronizing signals, a PLL can track an input frequency, or it can generate a frequency that is a multiple (or fraction) of the input frequency.
PLL circuits can be implemented in either analog only technology, or with digital components. By using digital components, the area consumed by a PLL can be reduced, lock time can be decreased, and programmability of the PLL for use at different frequencies can be easily implemented.
With reference to FIG. 1, a typical PLL 20 is now described. The PLL 20 receives a reference frequency signal Fref that is fed to a first input of a phase difference detector 22, which is illustratively a time to digital converter (TDC) phase detector. A second input of the TDC 22 receives a feedback frequency signal Fdiv. The TDC 22 determines a difference in phase between the reference frequency signal Fref and the feedback frequency signal Fdiv and outputs a digital signal Ddif indicative of that measured difference. A subtractor 24 receives the digital signal Ddif and subtracts from it the quantization noise Qnoise. The output from subtractor 24 is filtered by digital filter 26, which generates a control signal Dcont.
A digital-to-analog converter (DAC) circuit 28 converts the digital control signal Dcont to an analog control signal Acont. A control input of an oscillator circuit 18, which is illustratively a current controlled oscillator (CCO), receives the analog control signal Acont and generates an output clock signal Fcco having a frequency that is dependent on the magnitude of the analog control signal Acont. A divider circuit (/N) 32 divides the output clock signal Fcco by N to generate the feedback frequency signal Fdiv which is compared to the reference frequency signal Fref to control loop operation. When Fref matches Fdiv, the PLL 20 is said to have “locked”.
A sigma-delta modulator (SDM) 34 quantizes a frequency control word FCW to generate a control signal S for the divider circuit 32. The control signal S modulates the divider circuit 32 during operation to thereby cause a frequency of the output clock signal to be a fractional multiple of the reference frequency signal Fref.
The frequency control word FCW is subtracted from the output S of the SDM 34 by subtractor 36 to produce a raw error signal E, representing the quantization noise introduced by the quantization of the frequency control word FCW. The raw error signal E is accumulated by accumulator 38 to produce the quantization noise signal Qnoise, which, as stated above, is subtracted from the digital signal Ddif indicative of the measured difference in phase between the reference signal Fref and feedback signal Fdiv.
While this implementation provides for a digitally implemented fractional-N PLL, power consumption of the design may be undesirably high due to the TDC 22, and fractional spurs may be generated, leading to undesirable performance when generating certain frequencies of signal.
Therefore, further development of digital PLL circuits is needed.